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The first company to deliver an Interoperable PCell Library (IPL) with advanced passives and support for multiple EDA vendor tools will have a distinct advantage when competing for the next generation of chips aimed at consumer electronics. So, who will be the first to offer this IPL?
By Michael Ma
The foundry industry has made great strides forward in providing complete, accurate PDKs (process design kits) for analog and custom design. However, recent advances in database technology by the EDA industry have created an opportunity to provide interoperable PCell libraries, which would support layout tools from multiple vendors. Although this would be a great benefit for chip designers, it has not yet happened.
Among the first steps in analog and mixed signal chip design are selecting the target process, then contacting the foundry to obtain a PDK for that process. PDKs contain schematic symbols, simulation models, DRC decks, and PCells for the target process. However, some components of these kits such as PCells are developed to support tools from just one EDA vendor. Foundries cannot justify the cost of providing separate PCell libraries for every different layout tool in the market. Unfortunately, this means that the designer who wishes to use the PDK supplied by the foundry is limited to using the tools supported by that PDK. This restricts design flexibility, and limits designer's ability to choose best-in-class tools.
Database Interoperability is Now a Reality
Recently, the EDA industry has moved rapidly to standardize on the OpenAccess database from Si2. Cadence Design Systems, Synopsys, Mentor Graphics, Magma Design Automation, Silicon Canvas, AWR, Silicon Navigator, and many other EDA companies have driven the development of OpenAccess as an open source, high-performance and high-capacity database which allows true interoperability among tools from different vendors.
Many of the most widely used tools in IC design, such as Cadence Virtuoso, Mentor Calibre, and Silicon Canvas Laker already support the OpenAccess database, and more OpenAccess tools are released every month. For the first time, a database created in one vendor's OpenAccess tools can be read and edited by another OpenAccess tool without intermediate translation or streaming. This presents a significant opportunity to simultaneously simplify design tool integration overhead and improve design turnaround time.
Interoperable PCell Libraries are Not Yet Available
However, the PCell libraries necessary to support this level of interoperability are not yet available. Foundries still distribute PCell libraries in formats which support the layout tools of only one vendor. The economic justification for doing so no longer applies – an Interoperable PCell Library (IPL) can now support all OpenAccess tools.
IC designers would benefit tremendously from an IPL. When making early decisions about the design flow, they would not be limited to the tools from a single vendor. They would benefit from a flow with fewer translation steps: analysis tools such as Calibre could directly read databases created by layout tools such as Virtuoso and Laker. OpenAccess versions of each of these tools are available today, but this interoperable flow is not yet possible because of the lack of an IPL.
Creating an Interoperable PCell Library
The tools exist to create IPLs today. Ciranova provides a free tool based on open standards called PyCell Studio. Available for free download from Ciranova's web site, PyCell Studio can be used to create IPLs and layout generators which support OpenAccess tools from every vendor. Numerous OpenAccess tools including as Virtuoso, Calibre, Laker, Analog Office, and RDE Framework have already been validated for compatibility with PyCells created by PyCell Studio, and testing continues with new tools.
More important, users do not face any licensing barriers when using PyCells. Any user anywhere in the world is able to freely use PyCells without being required to purchase or manage licenses. There are no restrictions on PyCell development, distribution or usage.
Planning for the Future: Advanced PCells
In planning for upcoming deep submicron process technologies, foundries are describing a variety of new design rules such as via neighbor spacing rules, density rules and conditional rules. It may be quite difficult to deploy accurate PCell libraries which support these new rules using traditional approaches. One frequently cited example is the advanced passives required by the analog and RF functions for the consumer products driving so much process development. Few examples exist of spiral inductors, comb capacitors, and multi-fingered poly/diffusion resistors in PDKs created using traditional methods.
PyCell Studio can be used to build design-rule correct-by-construction PCells for these advanced passives and other desirable devices. Any process which provides advanced PCells such as these in an IPL will be very attractive to designers facing short design cycles for new consumer electronic products.
Who will be First?
The first company to deliver an IPL with advanced passives and other devices plus support for multiple EDA vendor tools will have a distinct advantage when competing for the next generation of chips aimed at consumer electronics. Customers will respond very positively to the flexibility and productivity such an IPL will provide. The question remains, who will be the first to offer this IPL?
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